Call for Papers [ PDF ] [ TXT ]

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on network-on-chip (NoC) innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to:

NoC Architecture and Implementation
  • Network architecture (topology, routing, arbitration)
  • Timing, synchronous/asynchronous communication
  • NoC reliability issues and solutions
  • Security issues and solutions in NoC architectures
  • Power/thermal issues at NoC un-core and system-level
  • Network interface issues and solutions
  • Signaling and circuit design for NoC links and routers
NoC for Intelligent Physical Systems
  • NoC design for Deep Learning
  • Mapping of existing and emerging applications onto NoC
  • NoC case studies, application-specific NoC design
  • NoC for FPGA, structured ASIC, CMP and MPSoC
  • NoC designs for heterogeneous systems
  • NoC for CPU-GPU and data-center-on-a-chip (DCoC)
  • Scalable modeling of NoC
  • Machine learning for NoC and NoC-based Systems
Communication Analysis, Optimization, & Verification
  • NoC performance analysis and Quality of Service
  • Modeling, simulation, and synthesis of NoC
  • Verification, debug and test of NoC
  • NoC design and simulation methodologies and tools
  • Benchmarks, experiences on NoC-based hardware
  • Communication-efficient algorithms
  • Communication workload characterization & evaluation
NoC at the Un-Core and System-level
  • Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoC
  • NoC for new memory/storage technologies
  • NoC support for processing-in-memory
  • OS support for NoC
  • Programming models for NoCs
  • Interactions between large-scale systems (datacenter, edge and fog computing) and NoC-based building blocks
Novel NoC Technologies
  • Optical, wireless, CNT, and other emerging technologies
  • NoC for 2.5D and 3D packages
  • Package-specific NoC design
  • Network coding and compression solutions
  • Approximate computing for NoC and NoC-based systems
Inter/Intra-Chip and Rack-Scale Network
  • Unified inter/intra-chip networks
  • Hybrid chip-scale and datacenter rack-scale networks
  • All aspects of inter-chip and rack-scale network design

Electronic paper submission requires a full paper, up to 8 double-column ACM (sigconf) format pages, including figures and references. The program committee will use a double-blind review process to evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Proposals for special sessions and demos are invited. Paper submissions and demo proposals by industry researchers or engineers to share their experiences and perspectives are also welcome.

New in 2021 Journal Special Issue: A selected number of accepted papers will be invited to be published in the ACM Journal on Emerging Technologies in Computing Systems, Special Issue on Next-generation On-Chip and Off-Chip Communication Architectures for Edge, Cloud and HPC.

Paper submission website: Submission Website

 

Important dates (Anywhere on Earth)

Abstract registration: May 14, 2021 May 31, 2021 June 4, 2021 June 9, 2021 June 11, 2021
Full paper submission: May 21, 2021 June 4, 2021 June 9, 2021 June 11, 2021
Notification of acceptance: July 23, 2021